Field of the Invention
The present application relates to a technical field of display, more particular to a GOA unit, a method for producing the same, and a gate driver circuit including the GOA unit.
Description of the Related Art
GOA (Gate Driver on Array) technique is one of gate driver techniques for liquid crystal panels, a basic concept of which is to integrate a gate driver circuit of the liquid crystal panel into an array substrate, so as to form a row scan driver for the liquid crystal panel. The GOA technique not only can save the cost, but also can achieve an aesthetic design of the liquid crystal panel to be symmetric for two sides thereof. It also can save up a welding area of the gate driver circuit, and thus can obtain a narrow frame design.
In the prior art, FIG. 1 is a schematic top view of a GOA unit. As shown in FIG. 1, the GOA unit includes a TFT (Thin Film Transistor) module and a capacitor module. FIG. 2 is a schematic sectional view of an area 01 along a line A-A′ and an area 02 along a line B-B′ in FIG. 1, taking a bottom gate type TFT as an example. As shown in FIG. 2, a method for producing the GOA unit is to manufacture a gate 111 on substrate 10 in a first conductive layer pattern, a first electrode 112 on substrate 10, an insulation layer 12, a semiconductor layer 13 and a source electrode 141, a drain electrode 142 and a second electrode 143 in the second conductive layer pattern in sequence. There is a channel 144 between the source electrode 141 and the drain electrode 142, and the first electrode 112 and the second electrode 143 form a capacitor structure.
When the second conductive layer pattern of the TFT module is manufactured in the prior art, one commonly used method is to expose a conductive layer coated with photo resist by a mask and then develop it, so that the photo resist at a region corresponding to the second conductive layer pattern is fully reserved, the photo resist at a region corresponding to the channel 144 of the TFT module is half reserved, but the photo resist at other regions is fully removed; and the conductive layer and the semiconductor layer 13 at the region where the photo resist is fully removed are etched away. However, when a layer of the photo resist is exposed by the mask and developed, as the development operation proceeds, it is necessary to reduce a thickness of the photo resist of the region corresponding to the channel 144 where the photo resist is half conserved, and it is necessary to keep a constant thickness of the photo resist of the region corresponding to the second electrode 143 where the photo resist is fully reserved. Since the second electrode 143 is of an integral structure having a relatively large area, the photo resist corresponding to the second electrode 143 is of an integral structure. Due to this, more developer liquid will flow toward the channel 144 having the photo resist of small thickness. It will cause amount of the developer liquid at the photo resist of the region corresponding to the channel 144 to increase. In this way, too much developer liquid accumulated at the region corresponding to the channel 144 will develop the photo resist of the region corresponding to two sides of the channel 144, and thus a part of the photo resist at the source and drain electrodes 141 and 142 where the photo resist is fully reserved is developed and removed. Furthermore, in the subsequent etching process, a part of the conductive layer and the semiconductor layer 13 located at the region where the part of the photo resist is developed and removed at the source and drain electrodes 141 and 142, is etched away. Consequently, the source and drain electrodes 141 and 142 are narrowed while the channel of TFT is widened.